Velodyne Lidar provides smart, powerful lidar solutions for autonomy and driver assistance. Headquartered in San Jose, CA, Velodyne is known worldwide for its portfolio of breakthrough lidar sensor technologies. Our lidar technology has revolutionized perception and autonomy for automotive, new mobility, mapping, robotics, and security applications. Our mass-market adoption has created new opportunities in the software space, and we are currently developing a suite of new services.

Velodyne Lidar is looking for a Staff ASIC Digital Engineer to work on custom ASICs for lidar signal processing.  In this role, you will work on architecture and implementation in the areas of digital design and FPGA integration of custom ASICs.  You should have hands-on experience with complex ASIC and SOC designs for real-world product designs. 

You will be an important member of asic development, collaborating with other disciplines of analog ASIC design, FPGA, HW and FW engineers to come up with specs for the product and implement them from RTL to GDS. 

Job Responsibilities:  

  • RTL design of datapath, calibrations and control intensive digital blocks
  • Embedded FPGA configuration and integration into existing systems
  • Collaborate with system architects, algorithm developers, and analog designers to define innovative digital functions.
  • Perform digital design work across all aspects of the design flow from RTL to GDS.
  • Perform thorough verification planning and work with cross-functional teams for successful chip design and bringup.
  • Develop synthesis constraints and co-ordinate with backend teams.
  • Work with analog designers for mixed-mode simulation setup and debug.


Job Requirements:  

  • Hands-on and recent experience with high speed mixed-signal digital design in FPGA & ASIC
  • Experience with mixed-signal IP integration and development
  • Perform or analyze Static Timing Analysis (STA) reports, clock domain crossing, Logical Equivalency Checks etc.
  • Experience with using tools such as Cadence/Synopsis/Quartus for digital design and able to use virtuoso analog environment.
  • Experience with project management tools (Jira, Bitbucket, Confluence, etc.)


Preferred Education and Experience Requirements:  

  • BSEE, MSEE or PhD with 5+ years of relevant experience in Digital ASIC design and integration
  • Experience with signal processing a plus.
  • Experience with automotive development processes is a plus.


Note to all recruitment agencies: Velodyne Lidar does not accept agency resumes. Please do not forward resumes to our career page or any Velodyne employees. Velodyne is not responsible for any fees related to any unsolicited resumes.

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