Sr Staff Engineer, SoC Digital Design, Synthesis, UPF, Constraints
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are seeking a skilled Digital Design Engineer with a strong focus on synthesis, Unified Power Format (UPF), and constraints management. The ideal candidate will have experience in the full ASIC design flow, including synthesis, timing closure, with a particular emphasis on power intent and constraint development.
This role is hybrid based out of Toronto, Ottawa or Boston.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Responsibilities:
- Develop and implement RTL designs for high-performance digital IPs, ensuring alignment with architectural specifications.
- Define and manage design constraints to achieve optimal power, performance, and area (PPA) metrics.
- Collaborate with cross-functional teams, including architecture, verification, and physical design, to drive design convergence and meet project goals.
- Utilize UPF to specify power intent and manage power domains within the design.
- Perform logic synthesis and analyze synthesis results to ensure design meets timing, area, and power requirements.
- Deploy innovative techniques for improving power, performance, and area of the design, driving experiments with RTL and evaluating synthesis, timing, and power results.
- Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environments.
- Enhance RTL design environment, tools, and infrastructure.
Experience & Qualifications:
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of experience in digital design, with a focus on synthesis, UPF, and constraints management.
- Proficiency in hardware description languages (Verilog, VHDL) and experience with industry-standard EDA tools for synthesis and static timing analysis.
- Strong understanding of power intent specification using UPF and experience managing multiple power domains.
- Experience with constraint development and management to achieve timing closure in complex designs.
- Familiarity with the full ASIC design flow, including simulatin, synthesis, and timing closure.
- Excellent problem-solving and debugging skills across various levels of design hierarchies.
- Strong programming skills in scripting languages (e.g., Python, Tcl) for design automation.
- Ability to work collaboratively in a team environment and communicate effectively with cross-functional teams.
- Experience with high-frequency logic design and knowledge of processor architectures. (nice to have)
- Familiarity with advanced process nodes (e.g., 5nm and below) and associated design challenges. (nice to have)
- Experience with formal verification methodologies and tools. (nice to have)
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.
Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.
If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.
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