SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

NEW GRADUATE, SILICON ENGINEER

Are you an engineering student graduating in fall 2022 or spring/summer 2023 looking for full-time employment after graduation? We are looking for engineers to help us develop next generation silicon for SpaceX. The work will be pre-silicon RTL design, silicon bring-up (software development), chip verification, and physical chip implementation and verification using state-of-the-art tools and methodologies. The ideal candidate will be a hands-on self-starter who can execute the steps required to fully design and verify complex designs.

Full-time employment is available working on our Starlink program in Irvine, CA or Redmond, WA. 

RESPONSIBILITIES:

  • ASIC/FPGA Design & Verification
    • Participate in all phases of ASIC/FPGA design and verification flows
    • Contribute towards design architecture, RTL implementation and/or verification, and emulation
    • Bring-up and validate ASICs and FPGAs in the lab (write embedded software using C/C++ and/or Python)
    • Hands-on self-starter who can execute the steps required to fully verify a complex digital design
  • RF/Analog IC Design
    • Simulate and model RFIC systems at high level and work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains
    • Derive specifications for the RFIC subsystems and circuits
    • Develop RF/microwave circuits in state of the art SiGe or CMOS processes
    • Perform IC floor planning and layout
  • Digital Signal Processing
    • Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.)
    • Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers
  • Physical Design
    • Perform partition synthesis and physical implementation steps (e.g. synthesis, floor planning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
    • Develop/improve physical design methodologies and automation scripts for various implementation steps
    • Participate in silicon tapeouts in advanced technology nodes for future Starlink SOCs

BASIC QUALIFICATIONS:

  • Bachelor’s degree in an engineering discipline, mathematics or physics
  • Experience working with ASIC, FPGA, RF/RFIC, or SOC

PREFERRED SKILLS AND EXPERIENCE:

  • Understanding of computer architecture
  • Experience in one or more of the following areas:
    • Analog or digital CMOS integrated circuit design and/or physical design
    • SystemVerilog, Verilog, VHDL or C/C++
    • Using scripting languages, e.g. Python for automation
    • Object-oriented programming
    • Using simulation tools such as ADS, Spectre, HFSS or Momentum
    • RTL design, chip bring-up, verification, and/or post-silicon validation experience
    • Digital signal processing

ITAR REQUIREMENTS:

  • To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.

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