SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

PRINCIPAL SOC PHYSICAL DESIGN STA/TIMING ENGINEER (SILICON ENGINEERING)

As a member of our multifaceted ASIC team, you will have the rare and phenomenal opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, and empower humanity every single day with performance that far surpasses that of traditional satellite internet and ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.

In this critical role, as an SOC/ASIC back-end static timing analysis (STA) engineer, you will be collaborating with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge SOCs for customers on Earth and beyond. We are looking for people who want to dive in and get their hands dirty and push the limits of what is possible through innovation, determination, and teamwork.

RESPONSIBILITIES:

  • Develop/support automated block and full chip level advanced timing/noise signoff flows (with advanced and parametric on chip variation, and voltage drop aware STA)
  • Define block and full chip timing signoff criterion, methodology, constraints, modes and scenarios and close timing at multi-corner and multi-mode environments
  • Develop/support signoff STA timing/power optimization engineering change order flows and integrate them into physical design flow
  • Work with systems and architecture, SOC integration, verification, DFT, mixed signal, IP owners, synthesis, and place/route teams to address the design challenges in the context of timing sign-off
  • Generate block timing begets, clock and I/O context files
  • Debug and drive fixing of constraint correlation issues between top and block level
  • Develop clock network simulation and jitter analysis methodologies
  • Drive custom IP integration, custom timing check flow enablement and closure until tapeout
  • Guide full chip team to plan and build reference/special clock trees for minimal jitter and insertion delay
  • Develop and run block/full chip level noise analysis flows and drive the noise/signal integrity closure with block and full chip engineers
  • Work with voltage drop, architecture, package teams to understand voltage drops, guard banding requirements, voltage and library selection for signoff STA and noise analysis

BASIC QUALIFICATIONS:

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 10+ years experience creating static timing analysis flows for SOC/ASICs

PREFERRED SKILLS AND EXPERIENCE:

  • Full chip and block level STA tapeout experience, constraint generation and partitioning
  • Knowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations, voltage drop aware STA, and clock reconvergence pessimism removal
  • Experience in IP integration (e.g. memories, I/Os, Analog IPs, SerDes, DDR etc.)
  • Experience in industry standard STA and Noise/Signal integrity analysis tools
  • Experience in clock jitter simulation and analysis methodologies
  • Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on physical design and timing closure
  • Deep understanding of ASIC synthesis and physical design flows and methodologies
  • Experience with high reliability design and implementations
  • Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile, etc.)
  • Familiar with implementation or integration of design blocks using Verilog/System Verilog
  • Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

  • Must be willing to travel when needed (typically <10%)

ITAR REQUIREMENTS:

  • To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.

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