SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. ASIC/FPGA DESIGN ENGINEER (STARLINK)
As a member of our multifaceted ASIC/FGPA team, you will have the rare and phenomenal opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, and empower humanity every single day with performance that far surpasses that of traditional satellite internet and ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.
In this critical role you will be developing silicon projects that are driving cutting-edge next generation ASIC/FPGA designs, and collaborating with world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering) for deployment of these projects in space and ground infrastructures. We are looking for people who want to dive in and get their hands dirty and push the limits of what is possible through innovation, determination, and teamwork.
Design digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks
Analyze architectural trade-offs based on features, performance requirements and system limitations
Define micro-architecture, implement or integrates design blocks using Verilog/SystemVerilog and deliver a fully verified, synthesis/timing clean design
Participate in all phases of ASIC and/or FPGA design flow (e.g. synthesis, timing closure, formality check and ECOs)
Participate in silicon bring-up for blocks owned
Bachelor’s degree in electrical engineering, computer engineering or computer science
5+ years of experience working with ASICs or FPGAs
PREFERRED SKILLS AND EXPERIENCE:
Ability to solve complex problems including clock domain crossings and power optimization
ASIC/SoC system integration experience
Experience with high reliability design and implementations
Experience with advanced silicon process and technology nodes for high speed and low power consumption
Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
Ability to work in a dynamic environment with changing needs and requirements
Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
Enjoys being challenged and learning new skills
Willing to travel when needed (typically <10%)
Willing to work extended hours and weekends as needed to hit critical milestones
This position can be based in Redmond, WA or Irvine, CA
To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.