As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
SiFive is expanding into the UK, providing a unique opportunity for strong candidates with a passion for innovation and product delivery to be part of this exciting new engineering team.
As an Automotive Safety RTL Design engineer at SiFive you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture. You will play an important role in taking these high-performance RISC-V cores into the rapidly expanding market for automotive applications of processor technology. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
- Architecting, designing and implementing automotive safety features within existing and new high performance RISC-V cores.
- Working with the safety manager and verification teams to measure and improve fault tolerance.
- Contributing towards the company’s safety culture.
- Ensuring that knowledge is shared via great documentation and participation in a collaborative design culture.
- Mentoring and advising other engineers within the team on automotive safety aspects of their work.
- Strong experience in automotive safety (ISO26262: ASIL-B and ASIL-D) and its application within ASIC designs.
- In-depth experience working on processor microarchitecture and RTL design.
- Expert in hardware (RTL) design in Verilog, System Verilog or VHDL.
- Experience with and/or interest in learning at least one object-oriented and/or functional programming language.
- Attention to detail and a focus on high-quality design.
- Ability to work well in a team and collaborate with colleagues worldwide.
- A Master's or PhD in EE, CS, CE or a related technical discipline and equivalent industrial experience.