As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
SiFive is looking for an engineering leader who is passionate about designing industry-leading interconnect and uncore IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating massively customizable IP and improving time-to-market by designing hardware as highly-configurable generators. We're leveraging technology and ideas from the software industry to execute hardware design with the agility of software development.
We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP using the Chisel hardware construction library embedded in the Scala language, and are seeking a motivated individual to lead a team in enhancing/evolving our existing IP as well as developing new IP.
Join us, and surf the RISC-V wave with SiFive!
- Manage and lead a team of hardware engineers to architect, design and implement an enhanced TileLink interconnect, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel
- Recruit new engineers into the team and mentor/develop existing team members
- Implement RTL generators such that elements self-configure to optimally connect to each other
- Enhance future designs to provide higher performance, more efficient multi-core and multi-system coherence
- Design extensive configurability in as a first-class consideration
- Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
- Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans
- Ensure that knowledge is shared via creation and maintenance of great documentation and foster a culture of collaborative design
- 10+ years of RTL design, development and leadership experience
- At least 5 years of engineering management experience, and collaborating with globally distributed engineering teams
- Experience with NoC or other chip interconnect fabrics and with industry-standard bus protocols (AMBA et al)
- Strong software engineering skills/background, including object-oriented, aspect-oriented, and/or functional programming
- Attention to detail and a focus on high-quality design
- Ability to inspire and motivate an engineering team and a belief that engineering is a team sport
- Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software is a plus
- Knowledge of one or more of: Chisel/Scala, RISC-V architecture, Git/Jira/Confluence is a plus
- BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience
SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off; flexible work environment; health, vision and dental benefits; 401(k) plan; employee stock option program, and much more.