As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
As a Reliability, Availability, and Serviceability (RAS) Architect, you will join our world-class architecture team to expand SiFive’s ability to efficiently provide RAS solutions for fault-sensitive markets. RAS solutions that are low cost to develop, deploy, and make available are exponentially growing in importance to our customers. This position is an opportunity to anticipate and solve RAS challenges in a truly unique and significant way; to impact RAS within SiFive and the wider community.
- Contribute to an overall RAS solution portfolio that is seamless, coherent, and extensible.
- Extend the RAS solution set across a widely configurable IP and unique development environment.
- Develop and extend RAS metrics to better assess current behavior and identify high priority RAS capability and solution gaps.
- Develop RAS solutions to close gaps in the RAS solutions and ensure deployment, as appropriate, across a wide product portfolio.
- Collaborate with market specific architects to generalize specific solutions to apply them to other markets.
- Collaborating with the Engineering teams to ensure optimal implementation of the defined fault mitigation solutions within individual IPs and across multiple connected IPs.
- PhD or 5+ years of experience in RAS
- Strong architectural background with experience in working with customers, engineering, and validation teams.
- Experience with SoC and IP design flows from requirement definition and architectural design to physical implementation.
- Familiarity with advanced CPU architectures and pipelines, and interconnect architectures.
- Excellent analytical, written, and verbal interpersonal skills and ability to work as part of a worldwide team.
- Strong mathematical and analytical skills with experience in assessing and projecting how users experience faults.
- Master's or PhD in a related technical field, e.g. computer science, electronic/computer engineering, etc.