As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.
As an ALU/FPU Design Engineer at SiFive, you will be part of a global team designing the best CPU cores in the world, based on the revolutionary open RISC-V architecture. You will master the art of designing hardware as configurable generators in a hardware-enhanced software language. You will be working in a fast-paced dynamic and outstandingly productive environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
- Designing, implementing and enhancing arithmetic units for RISC-V CPU Core generators in Chisel.
- Architecting shared arithmetic units; combining capabilities for double/single/half-precision floating point, integer and/or fixed-point operations.
- Designing in maximum configurability as a primary consideration, including reuse of arithmetic units for vector and scalar operations.
- Mastering and contributing to SiFive's innovative development flow.
- Performing initial sandbox verification, collaborating with the verification team to create verification plans and supporting verification closure.
- Ensuring that knowledge is shared via great documentation and a participation in a culture of collaborative design.
- 2+ years of recent industry/academic experience related to the fields of Computer arithmetic/architecture.
- Prior experience designing high-performance arithmetic units.
- Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL.
- Experience with Scala and/or Chisel is a plus.
- Willingness to learn Scala and Chisel is a must.
- Knowledge of at least one object-oriented and/or functional programming language is a plus.
- Attention to detail and a focus on high-quality design, as expected from a successful design engineer.
- Ability to work well with others and a belief that engineering is a team sport.
- Masters or PhD in EE, CE, CS, Math or a related technical discipline; or equivalent experience.