As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
In this position, you will drive the redesign of the software in our FPGA-accelerated simulation infrastructure which employs cloud-hosted PCIE-attached FPGAs to rapidly evaluate new RISC-V core designs. We’re looking for a self-directed engineer who can use their experience writing performant code for PCI-E-based FPGAs and building scalable applications in C++ to take our infrastructure, based on FireSim (https://fires.im), to the next level. With your help, we aim to build the next generation of hardware emulation capacity for our RISC-V core IP: fast to support RISC-V software development, productive to debug, and cost-effective, so that it can be deployed to every engineer in the company.
- Redesign the software-component of Firesim infrastructure.
- Optimize PCI-E performance to improve throughput.
- Co-design FPGA RTL and simulator compiler subsystems.
- Work with SiFive engineers to build out new emulator features.
- Strong experience writing C++ (> 8 years as a primary language).
- Experience with designing standalone applications / libraries.
- Experience with developing PCI-E applications (Ideally, for FPGAs over PCI-E).
- Self-directed. Strong oral and written communication skills.
- BS in Computer Engineering, Computer Science, or Electrical Engineering.