As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
• Architecting test methodologies applicable to a wide range of CPU designs for CPU
memory sub-systems including memory virtualization (Paging and Hypervisors), LoadStore unit, various levels of caches and industry standard bus protocols (e.g., AMBA and
• Creating effective verification strategies for CPU memory system caches.
• Building test plans to implement these strategies, considering issues such as design
feature priority, potential customer impact, coverage metrics generation and
• Developing tools, test benches, and test suites (UVM, C++/C or otherwise, as needed)
to execute test plans.
• Developing and using unit level test benches that use constrained random stimulus.
• Using assembly code Random test generators to meet verification objectives in single
and multi-core CPU environments.
• Writing directed assembly tests as appropriate to test CPU functions.
• Collaborating closely with the design team on feature specifications, test plans and
• 3-8 years of recent experience with standard verification tools and methodologies (C,
UVM, Verdi/DVE, System Verilog, Verilog, Make files, scripting languages, etc.),
especially in hands-on testbench development and test suite generation.
• Solid understanding of CPU and SoC memory architecture including memory
virtualization (hypervisor, paging), Load-Store unit, various levels of caches, cache
coherence protocols, bus interface units, and memory controllers.
• Experience with industry standard system bus protocols (e.g., CHI, ACE, AMBA AXI,
AHB, APB) is preferred. Knowledge of Tilelink is a plus.
• A thorough understanding of the high-level verification flow methodology (test plan
generation, test generation, failure analysis, coverage analysis and closure).
• Ability to effectively assess the design verification metrics, remaining state space to be
covered, and efficient methods to achieve verification closure.
• Verification experience in test planning, constrained random test generation, test
stimulus, code coverage, functional coverage.
• Ability to learn languages and methodologies that are not part of the industry standard to
verification (Scala, Chisel, etc.)
• Understanding of CPU memory systems caches from an architectural level.