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- Architect, design and implement an enhanced TileLink interconnect, protocol bridges, and other infrastructure/uncore logic as RTL generators, including both open-source and proprietary designs.
- Improve current designs and work on future designs to provide higher performance, more efficient multi-core and multi-cluster system coherence.
- Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of design collateral.
- Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
- Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.
- Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
- 5+ yrs of recent industry experience with coherent fabric, protocols for scalable multi-core and multi-cluster SoC designs.
- Experience with NoC or other interconnect fabrics.
- Experience with industry standard bus protocols (e.g. AMBA). Knowledge of TileLink is a plus.
- Knowledge of cache coherence protocols, architectures and concepts.
- Ability to architect solutions to connect bus fabrics of disparate protocols.
- Strong software engineering skills/background, including:
- object-oriented, aspect-oriented, and particularly functional programming;
- compiler infrastructures and data modeling for intermediate representations, particularly for domain-specific languages.
- Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Experience with Chisel, Bluespec, or other HDL for expressing configurable hardware via software is a plus.
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and a belief that engineering is a team sport.
- BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.