As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
SiFive is expanding into the UK, giving a unique opportunity for the right candidate to be part of this exciting new engineering team.
As a Lead Cache Subsystem Microarchitect and RTL design engineer at SiFive you will be part of a team of engineers who are passionate about designing industry-leading CPU cores and cache subsystems, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
- You will architect, design and implement new high performance cache subsystems in SiFive's RISC-V CPU core generators and enhance features and performance in existing ones.
- Working on the microarchitecture development and specification; ensuring that knowledge is shared via great documentation and participation in a collaborative design culture.
- Performing initial sandbox verification and work closely with the verification team to create and execute detailed verification test plans.
- Working with the physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
- Collaborating with the performance modelling team for performance exploration and optimization to meet performance goals.
- Relevant industry experience working on high-performance, energy-efficient cache subsystem designs, ideally within a CPU or GPU subsystem.
- A background of a successful cache subsystem development from architecture through tapeout.
- Expertise in multi-level coherent cache architectures and designs.
- Experience with TileLink or other similar interconnect architecture.
- Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL.
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and a belief that engineering is a team sport.
- A Bachelor's or Master's degree in EE, CE, CS or a related technical discipline, or equivalent experience.