As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.
At SiFive, we build a culture of hardware-software codesign to develop a highly optimized hardware and software IP that targets a wide range of applications and domains; our goal is to optimize the hardware and software solutions while keeping modularity and reuse. We are building the next generation technology in compute and parallel computing solutions. The framework engineer charter is to integrate SiFive software and hardware solutions into application frameworks and optimize the end-to-end performance and quality of these frameworks on SiFive solutions while leveraging the open-source software and hardware RISC-V echo system and contributing to it.
- MLIR-based parallel computing infrastructure development.
- Large scale application/middleware integration.
- Co-work with SW & HW members for performance exploring and tuning for SiFive platforms.
- 2+ years of Large Scale Software design and programming experience in C/C++/Python for development, debugging, testing, and performance analysis.
- Strong C++ programming skill.
- Basic understanding of Deep Learning.
- Experience with Heterogeneous computing frameworks (CUDA/Vulkan/OpenCL) is a plus.
- Familiarity with ML Runtime (TFLite/IREE/ONNXRuntime) is a plus.