SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.
Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.
We at SiFive are looking for a Performance Architect to join our growing team working on workload characterization of applications running on RISC-V cores. The candidate will need to have understanding of computer architecture, micr-architecture as well as System software, benchmark software and profiling and monitoring tools. Hands-on Lab skills is a plus. Knowledge of competitive system such as ARM and APPLE will round out the candidate..
Location: The ideal candidate for this position can work out of one of our US offices or remotely from home, collaborating with the HQ in San Mateo, CA. However, all positions are currently remote until further notice.
Person will be responsible for the workload characterization of applications running on RISC-V cores. They will need to have understand of computer architecture, micro-architecture as well as System software, benchmark software and profiling and monitoring tools. Hands-on Lab skills is a plus. Knowledge of competitive system such as ARM and APPLE will round out the candidate.
- CPU Performance benchmarking using silicon, RTL simulators or performance models
- Workload performance analysis in the areas of optimal source code, efficient compilation and bottleneck analysis
- Desirable: Workload characterization and workload reduction techniques for performance simulation
- Desirable: FPGA or ASIC synthesis, place and route, develop strategies and constraints to enable near complete utilization of available FPGA resources.
- Desirable: FPGA debug, including use of Integrated Logic Analyzer for waveform capture and debug
- Ability to build Linux, root file systems and modify boot code ( cross and native compile experience)
- Deploying bare metal workloads on silicon boards for the purpose of performance measurement and board tuning
- Knowledge of SPEC, SPECrate, EEMBC, MLPerf, other standard benchmarks, and/or vector benchmarks
- Desired: SimPoint analysis, workload characterization, and workload reduction through BBV and statistical analysis
- Desired: Python and TCL scripting for workflow automation.
- Familiar with git or other source code control system.
- Strong background with Linux-based development environments including python/shell programming.