As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.
Person will be responsible for the workload characterization of correlation of code snippets running on RISC-V cores. They will need to have understand of computer architecture, micro-architecture as well as system software, benchmark software and profiling and monitoring tools. Candidate needs to be knowledgeable about RTL simulations and performance models. Knowledge of competitive system such as ARM and APPLE will round out the candidate.
- Strong foundation in computer architecture of CPU designs. Awareness of known industry micro-architectures is a plus.
- Ability to independently analyze performance bottlenecks in micro-architecture and software stack.
- Ability to design microbenchmarks to test specific microarchitecture features
- Ability to analyze the performance result to root cause the micro-architecture difference of design and model
- Ability to work independently, but also provide clear progress readouts throughout
- Familiar with RISC-V vector extension is a plus
- Familiar with C++ is a plus
- Familiar with the out-of-order CPU micro-architecture is a plus
- Good presentation skills
- Familiar with git or other source code control system
- Strong background with Linux-based development environments including python/shell programming