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As a Design Verification Engineer, you will work with CPU designers, compiler team, performance team, and system verification team to generate the test cases automatically to fit those teams verification requirements in different perspectives. Your responsibilities will target establishing a random instruction test generator that produces self-checking direct test cases.
- Review and influence product definition and specifications from a verification perspective and collaborate closely with the design team on feature specifications, test plans, and failure analysis.
- Develop checkers and assertions to verify the memory subsystem designs with interconnect.
- Develop tools, test benches, and test suites (UVM, C++/C, or otherwise as needed) to execute test plans.
- Write functional coverage, analyze both code and functional coverage, and close coverage holes.
- A minimum of 3 years of recent experience with standard verification tools and methodologies (SystemVerification/UVM, Verdi/DVE, Verilog, Makefiles, scripting languages, etc.).
- Familiarity with and/or ability to learn languages and methodologies that are not part of the industry-standard approach to verification (Scala, Chisel, etc.).
- A conscientious and thorough approach to Design Verification.
- Solid understanding of processor and SoC architecture, or a strong desire and ability to learn the same.
- A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure).
- Experience with prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms will be a plus.
- Good interpersonal skills to listen to diverse points of view and influence people from different disciplines.
- An unwavering dedication to product quality.