NeuroBlade is looking for a Verification Engineer to join our fast-growing engineering team.
We are looking for brilliant and passionate people to join us and play a major role in building the next big thing in AI! If you enjoy working on cutting edge technologies and solving complex problems, and  have a team spirit and a can-do-attitude – Your place is with us!

NeuroBlade set out on a mission to redefine computer architecture for memory intensive tasks. We build high performance solutions for the rapidly growing AI & Analytics market while lowering total cost of ownership.
NeuroBlade’s unique hardware solution paired with a complete end-to-end SW stack, enables businesses to take the next leap forward by increasing the efficiency and affordability of their data-centers.

What will you be doing :

  • Build UVM verification environments from scratch
  • Hunt for bugs in state of the art designs, both in block level and full chip
  • Gain full visibility to the design , and SW-HW integration

Requirements:

  • At list 2 years of experience with System-Verilog (or equivalent) environments
  • BSC EE-engineer/Computer-science
  • A team player, quick learner , good multitask ability , self managed
  • Scripting knowledge : TCL/Perl/Phyton/Other

Advantages:

  • Knowledge with Analytics & AI and processors design
  • Knowledge with UVM
  • Experience with FPGA systems and tools (Quartus, Vivado)
  • Experience with RTL design
  • Experience with lab work

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