About InnoPhase, Inc.
INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications.
Are you looking to grow your career at a company that 93% of our current staff approve of our leadership, values, and goals?
To learn more about InnoPhase, check out InnoPhase's ceritification profile at GreatPlacetoWork.com and our website at www.innophaseinc.com.
Staff Engineer, FPGA System Design (Contract to Hire): You will be responsible for contributing in developing novel/game-changing cellular infrastructure radio Front Haul Gateway (FHGW) FPGA and ASIC solutions. You will be responsible for solutions features, device functional specifications, and performance to deliver production quality programmable logic designs with embedded Linux based wireless communications software to enable our market leading cellular infrastructure radio solutions.
This full-time position is based in Irvine, CA.
Key Responsibilities
- Work with a team of SW engineers to define, develop and verify embedded Linux based SW for Cellular base station radios on custom FPGA designs including Applications and Drivers for embedded Linux-based environment and follow-on ASIC solutions.
- Establish unit level design, implementation, and test strategies
- Perform Synthesis, P&R and generated FPGA images
- Bring up emulation platform with SW and system teams
- Support integration and test, and debug software for timely closure
- Individual contribution is also required along with technical leadership and mentorship
- Develop and own functional blocks to be used on multiple platforms
- Hands-on debug capability using lab equipment and JTAG
- Contribute to/review specifications and architectures
- FPGA front-to-back digital design and verification – RTL through physical implementation
Job Requirements
- BS in EE/CS or equivalent required
- Eight or more years’ of working with FPGA development, implementation, and verification
- Develop FPGA design specifications, communicate and verify these specifications with the RF/FW designers
- Debug designs and provide timely closure
- Perform Synthesis, P&R and generated FPGA images
- Experience with embedded systems, wireless protocols, power management, signal processing and standard digital interfaces
- RTL design knowledge (Verilog/VHDL) and SystemVerilog
- Knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
Compensation and Benefits:
At InnoPhase, our compensation package includes base pay and pre-IPO stock options. The base pay range for this role is between $130K-$190K. Your base pay will depend on the market, interview results, skills, qualifications, experience, education, and location. Our employee benefits include a comprehensive group health plan, matching 401(k), training reimbursement, and various paid leaves (vacation, sick, holidays, maternity/paternity leave, jury). Visit our website to learn more about our employee benefits.
