About InnoPhase, Inc.
INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications.
Are you looking to grow your career at a company that 93% of our current staff approve of our leadership, values, and goals?
To learn more about InnoPhase, check out InnoPhase's ceritification profile at GreatPlacetoWork.com and our website at www.innophaseinc.com.
As Technical Lead – Design Verification, you will be the key contributor of ORAN SoC product design verification team and collaborate with FW & design team for product requirement definition, micro architecture study. You will participate in the verification of novel ORAN SoC functional blocks for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations. Beyond the technical contribution, you will also interface with functional leads in project coordination for schedule tracking on deliverables and dependencies. You also will provide technical advice to young engineers to ensure the quality of work. This role is an excellent opportunity for engineers with 10+ years of industrial experience to grow their technical career as well as leadership to climb up corporate ladders and join the exciting cellular product market space.
This position will be based in Bangalore, India.
Key Responsibilities:
- Develop testbench environment to perform verification of the design at IP/ Subsystem and SoC Level using SystemVerilog and UVM
- Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs
- Develop and execute verification plans based on design specifications and collaboration with architects and designers
- Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases
- Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification
- Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals
- Assist in emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell
Job Requirements
- Master's and/or Bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS
- 10 or more years of experience in design verification with proven experience in full chip verification from test plan development to tape-out sign-off
- Good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
- Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch
- Proficient in SystemVerilog, Verilog/VHDL, UVM and C; and scripting languages like Python, Perl and Tcl/Shell
- Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based test bench environments, writing SystemVerilog Assertions (SVAs), with embedded software design and testing
- Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB etc)
- Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus
- Track record of successfully executing block or chip-level verification plans
- Excellent communication and presentation skills, energetic and self-motivated
- Work effectively with an off-site/ offshore design and verification teams across locations
