You will collaborate with a multi-disciplinary team to deliver complex SOCs. The role will involve working with the design team to develop and implement chip DFT architectures; define strategy and requirements for block level and chip level testing infrastructure; interfacing with the design verification team to integrate DFT, verify and review coverage; and work with the test engineering team to bring up test patterns, debug and verify post silicon test functionality.

Qualification/Required Skills:

  • BS/MS in electrical engineering, computer engineering or related field.
  • Minimum 5+ years of relevant experience in large processors and/or SoC designs.
  • Proficiency in developing and implementing DFT architectures.
  • Experience with hierarchical scan design, scan insertion, scan compression and scan verification.
  • Familiarity with Memory BIST pattern generation, insertion and validation.
  • Experience with ATPG and functional pattern generation and simulation.
  • Experience in the creation and maintenance of DFT timing constraints.

Preferred/Beneficial Skills:

  • Experience in logic design, synthesis and gate-level simulations.
  • Understanding of mixed-signal circuit design and test strategies.
  • Experience debugging test failures in the ATE environment.
  • Experience with Boundary scan design.
  • Experience Debugging SDF based simulations.
  • Experience in post silicon test pattern diagnosis and test time reduction.

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