You will work closely with the design team to define strategy and requirements for block-level and chip-level testing infrastructure. With a thorough understanding of design intent, you will drive the verification environment and the creation of test plans for unit-level and chip-level verification, implement test benches and test vectors, and debug failures.

Qualification/Required Skills:

  • MS/PhD in electrical engineering, computer engineering or related field.
  • Minimum 10+ years of hardware verification experience.
  • Solid understanding of high-performance microprocessor architecture concepts with emphasis on caches, virtual memory, coherency.
  • Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools.
  • Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM.
  • Experience generating test vectors and debugging failures.
  • Experience analyzing coverage to meet product quality requirements.
  • Programming experience in languages common to the industry (e.g., C, C++, Perl, Python).

Preferred/Beneficial Skills:

  • Experience with UVM RAL methodology.
  • Experience in formal verification methodologies.
  • Experience with continuous integration tools, such as Jenkins.
  • Previous experience in CPU/core design verification efforts.
  • Experience with analog/mixed-signal verification methods.


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