You will be involved in all aspects of the SoC design flow, including specification definition, implementation, and verification. You will perform logic design for integration of functional units and subsystems into full chip designs, RTL coding, and simulation for SoC’s. You will interface with a multi-disciplinary team across the entire design cycle, helping to drive all aspects of the SoC design flow from high-level design to synthesis, place and route, timing closure and power analysis.
- MS/PhD in electrical engineering, computer engineering or related field.
- 10+ yrs. of demonstrated experience and proficiency in high-performance digital-logic design and integration.
- Extensive experience in defining SoC architecture and design flows.
- Ability to write detailed design specifications and clean readable presentations.
- Strong experience in RTL design, design verification, and synthesis for high performance and low power.
- Proficiency in front-end RTL tools and design methodologies.
- Experience designing complex state machines & data-path logic
- Strong experience in static timing analysis and Verilog-simulation tools.
- Experience interfacing with physical-design team to support floor-planning, post-layout timing closure and ECOs.
- Experience working closely with verification and validation groups in testing of the IP blocks and other similar logic blocks.
- Experience with analog IP integration.
- PCIe high-speed interfaces.
- Experience with SoC-level clocking, reset, and power management.
- Experience with post-silicon lab bring up, evaluation, and debug.
- Familiarity with RTL synthesis and DFT / MBIST insertion.
- FPGA design experience.
- Programming experience in languages common to the industry (e.g., C, C++, Perl, Python).