DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly pivot to capture opportunities, so we operate using our own capital and trading at our own risk.
Headquartered in Chicago with offices throughout the U.S., Canada, Europe, and Asia, we trade a variety of asset classes including Fixed Income, ETFs, Equities, FX, Commodities and Energy across all major global markets. We have also leveraged our expertise and technology to expand into three non-traditional strategies: real estate, venture capital and cryptoassets.
We operate with respect, curiosity and open minds. The people who thrive here share our belief that it’s not just what we do that matters–it's how we do it. DRW is a place of high expectations, integrity, innovation and a willingness to challenge consensus.
We are currently seeking a FPGA Engineer to join one of our trading teams. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA designs.
- Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
- Facilitate software integration efforts by developing new APIs and optimizing low level code.
- Propose creative solutions to overcome FPGA/hardware/software limitations
- Liaise directly with software and other design teams
- Bachelor’s degree or higher, Computer/Electrical Engineering or Computer Science with 3+ years of experience within the field
- Solid Hardware Engineering experience with a focus on digital design for FPGAs or ASICs.
- Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation
- Strong skills in RTL logic design (Verilog and System Verilog) and verification
- Experience in FPGA design flow including synthesis, place & route, static timing analysis
- Knowledge of UNIX operating systems and system performance concerns
- Experience with multi-threaded programming and asynchronous frameworks
- Experience with the design of system-on-chip (SOC) architectures, memory & processor subsystems, networking, and peripheral interconnect is required
- In depth knowledge of the TCP/IP stack and on chip networking applications
- Experience with functional verification utilizing high-level methodologies (e.g. System Verilog) is a plus.
- Excellent research and data gathering skills
- Familiarity with higher level scripting languages such as Python and applications for automating data collection and design validation
- Strong system level debugging and data analysis skills
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