DRW is a technology-driven, diversified principal trading firm. We trade our own capital at our own risk, across a broad range of asset classes, instruments and strategies, in financial markets around the world. As the markets have evolved over the past 25 years, so has DRW – maximizing opportunities to include real estate, cryptoassets and venture capital. With nearly 900 employees at our Chicago headquarters and offices around the world, we work together to solve complex problems, challenge consensus and deliver meaningful results. It’s a place of high expectations, deep curiosity and thoughtful collaboration.
We are currently seeking a Lead/SeniorFPGA Engineer to join one of our trading teams. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.
Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
Research and evaluate a variety of cutting-edge FPGA hardware and technologies
Propose creative solutions to overcome FPGA/hardware limitations
Liaise directly with software and other design teams
Conduct lab debugging and characterization of new hardware
Bachelor’s degree or higher, Computer/Electrical Engineering with 3+ years of experience within the field; (Master’s degree or higher also counts for experience)
Solid Hardware Engineering experience, especially with FPGA
Highly autonomous with a can-do attitude able to lead an FPGA based project from system requirements to production
Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation
Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing Verilog
Experience in FPGA design flow including synthesis, place & route , static timing analysis is required
Experience with the design of system-on-chip (SOC) architectures, memory & processor subsystems, networking, and peripheral interconnect is required
Knowledge of the TCP/IP stack
Strong working knowledge of either XILINX or ALTERA FPGA design flow
Experience with functional verification utilizing high-level methodologies (e.g. System Verilog) is a plus.