We are currently looking for a Digital Design Verification Engineer to join our DiDi Autonomous Driving Hardware team. The candidate will be a key member of the team and will be responsible for defining verification flows and implementing test plans for existing and future functional blocks.

Job Description:
As a digital design verification Engineer, you will play a central role in building hardware prototypes and products utilizing FPGAs/SoCs. You will interact closely with systems and algorithms engineer to understand implementation requirements, and participate in design verification and bring-up of various functional blocks by writing assertions, test benches, test harnesses, etc. Your daily responsibilities include
● Collaborate with other team members in a dynamic environment to define new technology requirements and specifications.
● Deliver detailed test plans for verification of complex digital design blocks.
● Create verification environments with Systemverilog and UVM.
● Work closely with design engineers to create coverage measures and corner cases; identify design holes and deliver functionally correct functional blocks
● Perform synthesis, P&R and timing closure with FPGA vendor tools.
● Create and execute plans for platform bring-up, debug, and validation.
● Document and support test plans and reviews.

Qualifications:
● MSEE or above with 3+ years experience in design verification.
● In-depth knowledge in HDL, verification and computational logic design verification concepts.
● Experience using scripting languages for test automation.
● Hands on lab bring-up and debug experience. Familiar with lab instrument usage.
● Good communication skills and self-motivated.

Preferred Qualifications:
● 5+ years experience in design verification. Proficiency in Systemverilog and UVM.
● Knowledge of mainstream FPGA SoC architecture and design tools is a plus.
● Understanding of AMBA protocols (AXI Interfaces) is a plus.
● Knowledge of fixed point digital signal processing is a plus.

Apply for this Job

* Required