A.P.T Portfolio, a high frequency trading firm that specialises in Quantitative Trading & Investment Strategies.Founded in November 2009, it has been a major liquidity provider in global Stock markets. 

Responsibilities:
  1. Verifying VHDL/Verilog-based digital hardware design blocks. This will be accomplished using system verilog and python-based test benches and both on the simulator and on the board.
  2. Write test-benches, test cases and ensure complete coverage of design features.
  3. Work in a small team that takes responsibility to own the complete solution.
  4. Responsible for finding ways to become more productive, improve verification, along with measuring and monitoring your already-deployed solutions. To do this you will have to create and maintain scripts (usually python and C++)
  5. We connect to exchanges over Ethernet so understanding the details of network protocols and network infrastructure is a very important aspect of the job
  6. Experience in Hardware tools for RTL simulation is required and ability to work well in a Linux environment
  7. Bachelors, Masters, in Electrical Engineering, Computer Engineering, Computer Science or related technical field, experience working with FPGA/ASIC validating. testing, and verification module design.
  8. Interest and/or familiarity with the financial services industry is a plus.
Requirements:
  • 0-2 years of experience(Preferred colleges- IITD, IITM, IITB, IIT KGP, IITM, IITK, IITR, IIT BHU)
  • Any graduate or post graduate from CSE, EE & Mathematics background. 
Perks & Benefits:
  1. Competitive Compensation and Bonuses
  2. Group Medical Insurance
  3. Life & Accident Insurance
  4. 4 weeks of Paid Vacation
  5. 12 Sick Leaves
  6. Health Club Membership

APT Portfolio is an equal opportunity employer.

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