A.P.T Portfolio, a high frequency trading firm that specialises in Quantitative Trading & Investment Strategies.Founded in November 2009, it has been a major liquidity provider in global Stock markets.
Responsibilities:
- Verifying VHDL/Verilog-based digital hardware design blocks. This will be accomplished using system verilog and python-based test benches and both on the simulator and on the board.
- Write test-benches, test cases and ensure complete coverage of design features.
- Work in a small team that takes responsibility to own the complete solution.
- Responsible for finding ways to become more productive, improve verification, along with measuring and monitoring your already-deployed solutions. To do this you will have to create and maintain scripts (usually python and C++)
- We connect to exchanges over Ethernet so understanding the details of network protocols and network infrastructure is a very important aspect of the job
- Experience in Hardware tools for RTL simulation is required and ability to work well in a Linux environment
- Bachelors, Masters, in Electrical Engineering, Computer Engineering, Computer Science or related technical field, experience working with FPGA/ASIC validating. testing, and verification module design.
- Interest and/or familiarity with the financial services industry is a plus.
Requirements:
- 0-2 years of experience(Preferred colleges- IITD, IITM, IITB, IIT KGP, IITM, IITK, IITR, IIT BHU)
- Any graduate or post graduate from CSE, EE & Mathematics background.
Perks & Benefits:
- Competitive Compensation and Bonuses
- Group Medical Insurance
- Life & Accident Insurance
- 4 weeks of Paid Vacation
- 12 Sick Leaves
- Health Club Membership
APT Portfolio is an equal opportunity employer.
