Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.
Job Description/Responsibilities
The Hardware Engineering group in India is responsible for all SoC hardware and package design at Achronix. It develops and integrates high-speed serial and parallel interface PHYs and controllers, network-on-chip, clocking & reset, etc. The Hardware Engineering group is hiring a Manager, who will be responsible for leading overall SoC physical design at Achronix’s Bangalore site. The employee will lead a physical design team that will contribute to multiple IP design verticals including memory and GPIO subsystems, SerDes subsystems, NoC, configuration and fullchip. The employee should be a multi-tasker with an ability to view requirements at different levels of abstraction, and condense them to actionable plans. The employee must be prepared to get technically hands-on when required, and should be an expert in physical design, physical verification, reliability verification and STA. The employee should be proficient with Industry standard Physical Design tools, specifically Synopsys DC-ICC2/Fusion Compiler, Primetime, ICV as well as Ansys tools (Redhawk) for reliability verification.
Additionally, the employee will also be responsible for hiring, training and growing a high performing team.This a high visibility role, with critical responsibilities, and requires a high level of expertise and commitment, and very good communication and presentation skills. The employee should be self-driven, constantly looking to set the bar higher, and a driver of excellence!
The employee’s responsibilities will include the following:
- Manage the SoC physical design team, working with the individuals on their development and learning, and managing assignments to specific projects and subsystems
- Support senior management with resource allocation and scheduling
- Help drive methodologies and best practices across all SoC physical design, including subsystem and fullchip floorplanning, synthesis, P&R, physical verification, reliability verification, etc.
- Drive fullchip level physical design
- Own QA for physical design of all subsystems and fullchip
- Be prepared to execute Physical Design of individual blocks (hands-on work as an individual contributor) when the need arises
- Post-Si debug support
- Provide technical leadership to and mentor engineers to create a high performing team
- Participate in meetings with global teams spanning Systems, Software & Product Engineering
Skills
- Expertise in leading physical design of multiple complex designs like PCIe, GDDR6, chip-level busses, etc., for high performance chips in FPGA/ML/AI domain
- Very strong working knowledge of synthesis, P&R, Physical Verification, STA, and Reliability verification
- Proficient with Industry standard Physical Design tools, specifically Synopsys DC-ICC2/Fusion Compiler, Primetime, ICV as well as Ansys tools (Redhawk) for reliability verification
- Experience in managing a large team, skill development, as well resource allocation and project planning
- Excellent written and verbal communication skills
- Intrinsically driven, and always raising the bar
- Ability to take high-level complex and/or long-term goals, break them down to smaller goals and tasks, and plan them out. Must be able to see the big picture
- Thrives in a dynamic & fast-paced environment, with a pro-active mindset
- Works well with other teams and has a collaborative approach
- Experience in handling 350+mm2 chip designs is a big plus
- Experience with 7nm and below FinFet technologies
- Automation & scripting experience, especially in Python and/or Perl is a big plus
- Experience with post-Si bring-up & debug is a plus
Qualifications
- BS or MS and 12+ years of experience
- At least 6 years of experience in managing physical design teams and executing complex projects
- Previous experience in at least 5 product developments, in technical management and hands-on implementation roles
- Ability to influence and collaborate across various levels of the company including India and Hardware Engineering leadership, and Company HQ
