Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.

Job Description/Responsibilities

The successful candidate will engineer the physical implementation of blocks from RTL to GDS in advanced FinFet technology nodes (7nm/12nm/14nm/16nm) and below, sharing responsibilities across design and verification. Responsibilities include the following:

RTL synthesis, writing timing, area, and other relevant constraints
Floorplanning, power grid implementation, clock tree synthesis, place and route
Parasitic extraction and physical design verification
Static timing analysis, and timing closure
Lint, design for test, test coverage
EM/IR verification and logic equivalence/formal verification
Low-power design and power optimization
Collaborate with other members of the team to optimize design in context
Work with other team members to improve methodologies and flows
Support post-silicon product bring-up and debug, timing and power characterization

Required Skills

Experience with digital VLSI CMOS circuit design and physical design in advanced FinFet technology nodes
Experience with HDLs such as Verilog
Experience with industry-standard tools such as Design Compiler, ICC2, PrimeTime, Tetramax, RedHawk, ICV, Caliber LVS/DRC
Excellent debugging skills
Comfortable programming in a scripting language (e.g., Python or Perl) and writing full programs from scratch (e.g. 5000+ lines of code)
Familiarity with revision-control systems (e.g., Perforce, git)
Familiarity with using and/or designing FPGAs is a plus
Well organized, punctual, excellent communication skills; ability to operate without direct supervision; ability to collaborate with other team members

Education and Experience

MS in Electrical Engineering with 3-10 years experience

The compensation range for this position is $145,000 - $200,000. Salary ranges dependent on experience and location.

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Achronix is committed to full compliance with US export control regulations under the Export Administration Regulations (EAR). In order to ensure compliance, Achronix must determine US citizenship or US visa/immigration status of all prospective applicants for this position.

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Hardware Engineer - Physical Design

Job Description/Responsibilities

Required Skills

Education and Experience

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